The present invention relates generally to integrated circuits, and, more particularly, to an input/output cell for an integrated circuit.
Integrated circuits (ICs) including system-on-chips (SoCs) integrate various digital as well as analog components on a single chip. The SoC communicates with external components such as a dynamic random access memory (DRAM) and a dual data rate (DDR) memory as well as Ethernet and universal serial data-bus (USB) physical layers and includes input/output (I/O) cells that facilitate the communication between the SoC and the external components. The I/O cells perform various I/O operations, such as driving logic signals from the SoC to the external components, receiving and conditioning input signals from the external components, and providing electrostatic protection to the SoC.
The I/O cells have input interfaces for communicating with internal logic of the SoC and output interfaces for communicating with the external components. The I/O interfaces operate at different supply voltages that are generated by a switched-mode power supply (SMPS) inside the SoC. The I/O cells are of two types: fixed I/O cells (FIO) and general purpose I/O cells (GPIO). An output interface of an FIO cell operates at a fixed voltage level and an output interface of a GPIO cell may operate at multiple voltage levels. The GPIO cells that have output interfaces operating at the same voltage level and input interfaces operating at a SoC internal voltage level together comprise a GPIO cell bank. The internal logic of the SoC operates at the SoC internal voltage level. Similarly, the FIO cells that have output interfaces operating at a fixed voltage level of the supply voltage and input interfaces operating at the SoC internal voltage level together comprise a FIO cell bank.
The GPIO cells are configured to operate in different modes based on the voltage levels (hereinafter referred to as “peak values”) of the supply voltage at the corresponding output interfaces. A GPIO cell must be configured to a particular mode of operation that corresponds to a desired peak value of the supply voltage at its output interface before the supply voltage at its input interface reaches a corresponding supply detection threshold voltage level (hereinafter referred to as “GPIO_THRESHOLD”). The operation mode is determined by a logic circuit of the SoC that configures the GPIO cell to operate at the desired peak value at the output interface. The logic circuit generates binary values that correspond to the desired peak value of the supply voltage at the output interface and applies the binary values at voltage selection pins of the GPIO cell, thereby configuring the GPIO cell. The binary values must be received at the voltage selection pins of the GPIO cell before the supply voltage at the input interface of the GPIO cell reaches the GPIO_THRESHOLD.
When the SoC is powered-on, the supply voltage received at the I/O interfaces of the FIOs and GPIOs begins to ramp up from zero to the corresponding peak values, at different rates. Generally, the SoC internal voltage level is less than the voltage level at which the external components operate. Hence, the supply voltage at the input interface of the GPIO cell is less than the supply voltage at the output interface of the GPIO cell. In a generic power supply ramp-up sequence, a lower voltage is derived from a higher voltage, and hence, the higher voltage ramps up to a corresponding peak value before the lower voltage. Hence, the supply voltage at the output interface of the GPIO cell reaches a corresponding peak value before the supply voltage at the input interface of the GPIO cell ramps up to the GPIO_THRESHOLD. If the GPIO cell is not configured to the required mode of operation before the supply voltage at the input interface of the GPIO cell reaches the GPIO_THRESHOLD, the GPIO cell enters a non-determinant state and may be damaged.
FIG. 1 is a timing diagram that illustrates a generic power supply ramp-up sequence of a GPIO cell of the SoC. The input interface of the GPIO cell receives a first supply voltage VDDI from the SMPS and the output interface of the GPIO cell receives a second supply voltage IOVDD from the SMPS. At time t0, the SoC is powered on and the first supply voltage VDDI begins ramping up to the corresponding peak value. From time t0-t1, VDDI is less than the GPIO_THRESHOLD, hence, the GPIO cell is in the tri-state mode. The second supply voltage IOVDD ramps up faster than the first supply voltage VDDI due to the generic power supply ramp-up sequence, so the first supply voltage VDDI continues to ramp up when the second supply voltage IOVDD has reached its corresponding peak value. At time t1, the first supply voltage VDDI reaches the GPIO_THRESHOLD and the GPIO cell exits the tri-state mode. However, at time t1, the mode of operation of the GPIO cell for the desired peak value of the second supply voltage IOVDD has not yet been configured. At time t2, the first supply voltage VDDI reaches the corresponding peak value and the mode of operation of the GPIO cell gets configured. Hence, from time t1-t2, the GPIO cell is in the non-determinant state and prone to damage.
Several techniques may be used to overcome the above-mentioned problem. One technique is to implement dedicated SoC pads on the board on which the SoC is mounted. The binary values corresponding to the desired peak value of the second supply voltage IOVDD are sampled directly from the SoC pads to the voltage selection pins of the GPIO cells of the GPIO bank. Thus, the GPIO cells are configured when the first supply voltage VDDI is ramping up (and is less than the GPIO_THRESHOLD). However, the voltage selection pins of the GPIO cells in each GPIO bank require dedicated SoC pads, thereby increasing area and cost of the SoC. For example, if the SoC has five GPIO banks and the GPIO cells in each bank have three voltage selection pins, fifteen pads are needed to set the voltage selection pins and configure the GPIO cells.
Another technique is to implement a specific power supply ramp-up sequence (also referred to as power sequencing) that mandates the first supply voltage VDDI ramp up to the GPIO_THRESHOLD before the second supply voltage IOVDD ramps up to the corresponding peak value, which results in setting the voltage selection pins before the first supply voltage VDDI reaches the GPIO_THRESHOLD, which prevents damage to the GPIO cell. However, specialized power regulators for regulating the ramp-up time of the first and second supply voltages VDDI and IOVDD are required to implement the specific power supply ramp-up sequence, which further increases cost and design complexity of the board on which the SoC is mounted.
Therefore, it would be advantageous to have a system for protecting an I/O cell of a SoC, and that configures the I/O cell in a desired mode of operation before the supply voltage at an input interface of the I/O cell reaches a corresponding supply detection threshold voltage level.